Over the past fifteen years, malicious fault attacks on microprocessors and/or embedded electronic systems have grown from a crypto-engineering curiosity into a systematic adversarial technique against secure hardware and software. Fault attacks use well-chosen, targeted fault injection combined with clever system response analysis to break the security of the embedded electronic system. Traditional fault attacks assume a fault model derived from the fault injection technique, and infer internal system secrets by analyzing the observed faulty system response and a difference to the known correct result.
More recently, malicious faults have also been recognized as a source of side-channel leakage. These so-called biased fault attacks detect the onset of faults as a function of fault injection intensity and internal secret variables. The biased faults then test the value of the internal secrets using hypothesis testing. The biased fault attacks use fault models that are less strict than traditional fault attacks. The biased fault attacks underline the growing need for a comprehensive countermeasure against fault attacks in hardware and software. Moreover, defending software against fault attacks may be difficult as the faults may originate in underlying processor hardware that supports the software. In this regard, it may be desired to provide more robust and cost effective fault countermeasures that can recover the processor hardware from fault attacks.